1. Field of the Application
The invention relates to a clock data recovery circuit, and more particularly, to a clock data recovery circuit having two loops.
2. Description of Related Art
As for a high-speed serial transmission system, an original data signal undergoes attenuation and distortion in transmission. Therefore, a receiver of the transmission system often has to perform an appropriate recovery processing to the original data signal through a clock data recovery circuit. In terms of operation, the clock data recovery circuit may generate a periodic recovery clock signal, and may extract a recovery data signal from the original data signal through the recovery clock signal.
The circuit structure of the clock data recovery circuit may generally be divided into two types: one is a circuit structure with a reference clock signal, and the other is a circuit structure without a reference clock signal. In terms of the circuit structure with the reference clock signal, the conventional clock data recovery circuit often generates the reference clock signal by an on-chip oscillator, so as to lower hardware costs of the circuit.
However, a frequency of the on-chip oscillator often has an offset due to variations in process, voltage or temperature, and thus loops in the clock data recovery circuit are unable to be locked, thereby causing the clock data recovery circuit to extract incorrect data signals.